1. Field of the Invention
The present invention relates to a technique of an amplifier and particularly to a technique by which the gain in a resistance load differential amplifier is stabilized so as not to be influenced by variations in production conditions, temperature, and so forth.
2. Description of the Related Art
FIG. 1A shows a circuit configuration of a conventional resistance load differential amplifier. The circuit in FIG. 1A comprises transistors M101, M201 and M301, which are n-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and resistors R101 and R201.
In FIG. 1A, one of the terminals of each of the resistors R101 and R201 is connected to the corresponding drain of each of the transistors M101 and M201. The other terminal of each of the resistors R101 and R201 is connected to a power source Vdd. The respective sources of the transistors M101 and M201 are connected to the drain of the transistor M301, and the source of the transistor M301 is connected to the ground.
Signals INP and INM (which are differential signals input to the circuit of FIG. 1A) are respectively input to gates of the respective transistors M101 and M201. Signals OUTM and OUTP (which are differential outputs in the circuit of FIG. 1A) are respectively picked up at the connection node between the resistor R101 and the transistor M101, and at the connection node between the resistor R201 and the transistor M201. A bias voltage Bias is applied to the gate of the transistor M301 whose voltage determines the value of a current Iss flowing between the drain and the source of the transistor M301.
The circuit of FIG. 1A is configured as above. Accordingly, a differential pair is configured of the transistors M101 and M201 and the transistor M301 functions as a current source that determines the sum Iss of currents (i.e., tail current) flowing between the drain and the source of each of the transistors M101 and M201.
If it is assumed that a transconductance of the transistors M101 and M201 is Gm and a resistance value of resistors R101 and R201 is R, a gain Av of the circuit of FIG. 1A can be expressed by the equation below.Av=Gm×R  (1)
In other words, the gain Av has a directly proportional relationship with the product of the transconductance Gm and the resistance value R.
The transconductance Gm and the resistance value R vary when production conditions, temperature conditions or the like vary. If a circuit that is identical with the circuit of FIG. 1A is formed on a semiconductor substrate, variations of the transconductances Gm and variations of the resistance values R are essentially linked between the transistors or between the resistors.
Additionally, a circuit in which the gain Av has a directly proportional relationship with the product of the transconductance Gm and the resistance value R of the load resistance is not limited to being the circuit shown in FIG. 1A. The circuits having such a relationship will be explained below:
For example, a resistance load differential amplifier as shown in FIG. 1B is configured by connecting, in cascade, transistors M102 and M202 which are n-type MOSFETs to the transistors M101 and M201 in the circuit configuration shown in FIG. 1A. Specifically, this circuit is configured by inserting the transistor M102 to the connection node between the resistor R101 and the drain of the transistor M101 and inserting the transistor M202 to the connection node between the resistor R201 and the drain of the transistor M201. In addition, a constant voltage Vref is applied to the gate each of the transistors M102 and M202.
A circuit as shown in FIG. 10 is a mixer amplifier (mixer) for a resistance load. This circuit is configured by further adding, to the circuit of FIG. 1B, transistors M103 and M203 that are n-type MOSFETs. Specifically, this circuit has a configuration obtained by connecting the drain of the transistor M103 to the connection node between the resistor R201 and the drain of the transistor M202 and connecting the source of the transistor M103 to the connecting node between the source of the transistor M102 and the drain of the transistor M101 in the circuit of FIG. 1B, and then by connecting the drain of the transistor M203 to the connection node between the resistor R101 and the drain of the transistor M102 and connecting the source of the transistor M203 to the connection node between the source of the transistor M202 and the drain of the transistor M201 in the circuit of FIG. 1B. One of the two signals to be mixed is input to the gates of the transistors M101 and M201 as the differential signals INP and INM respectively. In addition, the other signal to be mixed is handled as differential signals LOP and LOM, the signal LOP being input to the gates of the transistors M102 and M202 and the signal LOM being input to the gates of the transistors M103 and M203.
Even in the circuits of FIG. 1B and FIG. 10, the gain Av of each circuit has a directly proportional relationship with the product of the transconductance Gm and the resistance value R.
In the resistance load differential amplifier in such a relationship, in order to stabilize the gain so as not to be influenced by variables such as are in a production condition and temperature, a circuit is proposed which creates a bias condition by which the transconductance Gm of the transistors constituting the differential pair has an inversely proportional relation ship with the resistance value R of the load resistance. This circuit is based on the idea that, if the transconductance Gm has an inversely proportional relationship with the resistance value R so as to satisfy following equation (2), the gain is constant even when the transconductance Gm and the resistance value R vary.Av=Gm×R∝(1/R)×R=Constant  (2)
As an example of the bias circuit as above, the circuit shown in FIG. 2 is proposed in the document below.
“Design of Analog CMOS Integrated Circuits” by Behzad Razzavi (US), Published in 2001 by The McGraw-Hill companies, Inc. pages 107-108, and pages 377-379.
The circuit of FIG. 2 comprises transistors M111 and M112 (which are n-type MOSFETs), transistors M113 and M114 (which are p-type MOSFETs), and a resistor R111. In this configuration, the transistor M112 is provided such that the transistor size ratio (the ratio between the gate width W and the gate length L of the transistor element) is K times the transistor size ratio of the transistor M111 (W/L)N. Furthermore, the transistor M113 and the transistor M114 are identical in their transistor size ratios (W/L)P. It is assumed that the resistance value of the resistor R111 is RS.
In FIG. 2, the drain and the gate of the transistor M111, the gate of the transistor M112, and the drain of the transistor M114 are connected. Accordingly, the transistor M111 is a diode-connected transistor. Additionally, the drain of the transistor M112, the drain and the gate of the transistor M113, and the gate of the transistor M114 are connected. Accordingly, the transistor M113 is also a diode-connected transistor.
Both sources of the transistors M113 and M114 are connected to the power source Vdd. The source of the transistor M111 is directly connected to the ground. The source of the transistor M112 is connected to the ground via the resistor R111.
In the above document, in FIG. 2, a current lout flowing from the source to the drain of the transistor M113 is equal to a current Iref flowing from the source to the drain of the transistor M114. Accordingly, the equation below is satisfied.
                    Iout        =                                            2                                                μ                  n                                ⁢                                                                            C                      ox                                        ⁡                                          (                                              W                        /                        L                                            )                                                        N                                                      ·                          1                              Rs                2                                              ⁢                                    (                              1                -                                  1                                      K                                                              )                        2                                              (        3        )            
In the above equation, μn is a constant value representing a mobility of carriers and Cox is a constant value representing a gate capacity.
Below, the input/output characteristic of a circuit in which the differential pair is constituted of MOS transistors is described:
A circuit shown in FIG. 3 comprises transistors M121, M221 and M321 which are n-type MOSFETs. In this configuration, the transistors M121 and M221 constituting the differential pair have the same transistor size ratio (W/L)N and the same transconductance Gm.
In FIG. 3, the sources of the respective transistors M121 and M221 are connected to the drain of the transistor M321, and the source of the transistor M321 is connected to the ground. Accordingly, the current that is the sum of a current Idp flowing through the transistor M221 and a current Idm flowing through the transistor M121 flows between the drain and the source of a transistor M321 as a tail current Iss. The value of the current Iss is determined based on the voltage Bias applied to the gate of the transistor M321.
In the above configuration, by means of a power source E221, a voltage of Vin+ΔVin/2 is applied to the gate of the transistor M221, and also, by means of a power source E121, a voltage of Vin−ΔVin/2 is applied to the gate of the transistor M121. Here, the voltage Vin is a common mode voltage, and the voltage ΔVin is a minimal differential voltage.
The above mentioned document discloses that when the minimal current is defined as ΔId=Idp−Idm, the transconductance Gm of the differential pair is expressed by the equation below.
                    Gm        =                                                            ∂                Δ                            ⁢                                                          ⁢              Id                                                      ∂                Δ                            ⁢                                                          ⁢              Vin                                =                                    1              2                        ⁢                          μ              n                        ⁢                                                            C                  ox                                ⁡                                  (                                      W                    /                    L                                    )                                            N                        ⁢                                                                                4                    ⁢                    Iss                                                                              μ                      n                                        ⁢                                                                                            C                          ox                                                ⁡                                                  (                                                      W                            /                            L                                                    )                                                                    N                                                                      -                                  2                  ⁢                  Δ                  ⁢                                                                          ⁢                                      Vin                    2                                                                                                                                          4                      ⁢                      Iss                                                                                      μ                        n                                            ⁢                                                                                                    C                            ox                                                    ⁡                                                      (                                                          W                              /                              L                                                        )                                                                          N                                                                              -                                      Δ                    ⁢                                                                                  ⁢                                          Vin                      2                                                                                                                              (        4        )            
In the above equation, when ΔVin is sufficiently small, the above equation (4) can be approximate to the equation below.Gm=√{square root over (μnCox(W/L)NIss)}  (5)
The tail current Iss in the circuit of FIG. 3 is made identical with the output current Iout in the circuit of FIG. 2. In other words, the equation of the current Iout expressed in the above equation (3) is substituted into Iss in the above equation (5). Then the equation below is obtained.
                                                                           Gm                =                                ⁢                                                                            μ                      n                                        ⁢                                                                                                                        C                            ox                                                    ⁡                                                      (                                                          W                              /                              L                                                        )                                                                          N                                            ·                      Iss                                                                                                                                              =                                ⁢                                                                            2                      ·                                              μ                        n                                                              ⁢                                                                                                                        C                            ox                                                    ⁡                                                      (                                                          W                              /                              L                                                        )                                                                          N                                            ·                                              2                                                                              μ                            n                                                    ⁢                                                                                                                    C                                ox                                                            ⁡                                                              (                                                                  W                                  /                                  L                                                                )                                                                                      N                                                                                              ·                                              1                                                  Rs                          2                                                                                      ⁢                                                                  (                                                  1                          -                                                      1                                                          K                                                                                                      )                                            2                                                                                                                                              =                                ⁢                                                      1                    Rs                                    ⁢                                      (                                          1                      -                                              1                                                  K                                                                                      )                                                                                                            (          6          )                    
In the above equation, because K is a constant value, the transconductance Gm of the differential pair has an inversely proportional relation ship with the resistor Rs. In other words, the relationship of this equation (6) satisfies the equation (2). Accordingly, the gain Av of the circuit of FIG. 3 is constant (not being influenced by variations of production conditions or variations of a temperature, etc.).
As described above, in the bias circuit shown in FIG. 2, the output current Iout is determined based on the transistors M111 and M112. As is obvious from FIG. 2, the transistors M111 and M112 operate around the ground potentials. However, the transistors constituting the differential pair in the resistance load differential amplifier are generally operated by the potential which is about a half of the power voltage.
Here, the basic equation below expresses the input/output characteristic of the MOS transistor.
                    Id        =                                                            μ                n                            ⁢                                                                    C                    ox                                    ⁡                                      (                                          W                      /                      L                                        )                                                  N                                      2                    ⁢                                    (                              Vgs                -                Vth                            )                        2                                              (        7        )            
In the above equation, Id represents a drain current, Vgs represents a gate-source voltage, and Vth represents a threshold voltage between the gate and the source.
The above equation (7) is the base of the above equations (3) through (6). Here, these respective equations are used based on the assumption that all the transistors that constitute the circuit have the same threshold voltage Vth. However, when the respective transistors have different operation potentials, the respective transistors have different threshold voltages Vth due to a substrate bias effect (body effect) or similar effects, and accordingly, the respective equations (3) through (6) are not precise.
As described above, because the transistors M111 and M112 in the bias circuit shown of FIG. 2 have the operation potential different from the operation potential of the transistors constituting the differential pair in the resistance load differential amplifier, the respective transistors have different threshold voltages Vth. Thus, in the circuit of FIG. 2, the respective equations (3) through (6) are not satisfied accurately, and as a result there is a problem in which the variation of the gain of the amplifier cannot be suppressed.